Status:

Finished updating artwork

Reviewing artwork with GDDS



Design review successful.  Found several issues.

  - Issues reported fixed.



Worked on FPGA architecture.  Received new files from GDDS.



Luca will look at HM schematic this week.





This week:

Need to get PO going for Manuf.

  - Waiting on finalized artwork

Need to get PO going for Assy.

  - Waiting on finalized artwork

Need to deliver register list to GDDS and PEBBPNP/SW







Risks:

BFT92 Transistor: Infineon not delivering part (now 3 months).

  - Engineer not responsive to requests from Trish or Teresa

  - We will buy a similar transistor from Newark.

  - Ordered new transistor (PNP-RF) that might be able to replace BFT-92



PCB Capacitor traces sometimes are too long and too thin

  - Working with GDDS to evaluate and fix this

  - Fixed most traces.



GDDS Funding for PMC



VHDL simulator

  - Aldec not willing to give University Discount

    - Since it is not in a classroom

  - Consider ModelSim

    - Integrates with Xilinx ISE

    - ModelSim XE available for xilinx edition software